The present invention relates to formation and structures for interlevel dielectrics in integrated circuit fabrication.
A high degree of planarization is essential in the fabrication of integrated circuits with multiple levels of interconnect. Application of spin-on glass, followed by global etch-back, is widely used in the industry to achieve the desired level of surface planarity. However, spin on glass ("SOG") and SOG etch-back technique are inadquate in a variety of situations where topologies with high aspect ratio and/or more topologies are encountered due to lack of planarization and/or sog cracks. (Spin-on glass deposition is an example of a "sol-gel" process, which has been used in the semiconductor industry for many years. The unprocessed spin-on glass material (available in numerous formulations) is a fluid material (actually a gel). After the liquid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off the excess material. The surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness. The liquid material is then baked, to drive off solvents and provide a stable solid silicate glass. See generally, e.g., Dauksher et al., "Three `low Dt` options for planarizing the pre-metal dielectric on an advanced double poly BiCMOS process," 139 J.ELECTROCHEM.SOC. 532-6 (1992), which is hereby incorporated by reference.)
In most cases, successful planarization of severe topologies is achieved by a single or double SOG deposition+etchback step in the following sequence:
a) a layer of dielectric is applied between the underlying surface and SOG. PA1 b) application of a layer of SOG and SOG cure; PA1 c) application of a second layer of SOG and SOG cure (optional); and PA1 d) SOG etchback. PA1 a) Conventional dielectric deposition is applied (optional); PA1 b) Application of a layer of SOG and SOG cure (as in prior art); PA1 c) deposition of a layer of dielectric such as TEOS/ozone deposition, or PA1 d) application of a second layer of SOG and/or SOG cure: and PA1 e) SOG etchback.
However, in extreme topologies, when the volume of SOG is very large, shrinkage of SOG during planarization and post-planarization processing leads to formation of undesirable cracks or voids.
The proposed method seeks to alleviate the problem of SOG cracking by performing the following operations:
simple plasma-enhanced-TEOS (tetraethoxysilane, which is a popular and convenient feedstock for deposition of oxides from the vapor phase), or plasma-enhanced-silane oxide with or without dopant can be used to adjust for etch back selectivity between SOG and dielectric. Thicknesses between 1000 .ANG. to 5000 .ANG. can be used.
This process will leave a layer of dielectric between the 1st and the 2nd SOG layers in locations where conventional planarization technique are likely to crack or void. This provides enhanced reliability.
The thickness of the first SOG layer can be reduced to avoid any undesired effects, such as field inversion of underlying devices or enhanced hot-carrier injection. (See, e.g., Lifshitz et al., "Hot-carrier aging of the MOS transistor in the presence of spin-on glass as the interlevel dielectric," 12 IEEE ELECTRON DEVICE LETTERS 140-2 (March 1991), which is hereby incorporated by reference.)
A positive sloped valley is produced for second dielectric deposition. The step coverage will be enhanced due to this positive slope.
The structure provided by these steps has improved resistance to cracking, and improved resistance to other undesirable possible effects of thick spin-on glass layers.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure; applying and curing spin-on glass, to form a first dielectric; depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer; applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; performing a global etchback to substantially remove said dielectric stack from high points of said partially fabricated structure; deposition of an interlevel dielectric; etching holes in said interlevel dielectric in predetermined locations; and depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure; applying and curing spin-on glass, to form a first dielectric; depositing silicon dioxide under vacuum conditions, to form a second dielectric layer over said first layer; applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; performing a global etchback to substantially remove said dielectric stack from high points of said partially fabricated structure; deposition of an interlevel dielectric; etching holes in said interlevel dielectric in predetermined locations; and depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure; applying and curing spin-on glass, to form a first dielectric layer; depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer, said second dielectric layer having a thickness equal to or less than said first layer; applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers, said third dielectric layer having a thickness equal to or greater than said second layer; performing a global etchback to substantially remove said dielectric stack from high points of said partially fabricated structure; deposition of an interlevel dielectric; etching holes in said interlevel dielectric in predetermined locations; and depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit, comprising: an active device structure, including therein a substrate, active device structures, isolation structures, and one or more patterned thin film conductor layers including an uppermost conductor layer; and a planarization structure, overlying recessed portions of said active device structure, comprising a layer of sol-gel-deposited dielectric overlain by a layer of vacuum-deposited dielectric overlain by a further layer of sol-gel-deposited dielectric; an interlevel dielectric overlying said planarization structure and said active device structure, and having via holes therein which extend to selected locations of said uppermost conductor layer; and an additional thin-film patterned conductor layer which overlies said interlevel dielectric and extends through said via holes to said selectred locations of said uppermost conductor layer.